As the semiconductor industry develops continuously, semiconductor fabrication processes have stepped into the nanometer age. In compliance with the trend that various electronic products become smaller and smaller with more and more powerful capabilities, a fabrication procedure with an original line width of 0.18 μs has advanced to that with a current line width of 0.13 μs or even 90 nm and 65 nm.
Accompanying such a trend that a chip is provided with more and more powerful capabilities and a semiconductor element is made smaller and smaller, more and more demanding technical requirements have been imposed on various phrases in the fabrication procedure. Due to the smaller element and more complex internal circuits, the fabrication procedure becomes more sensitive to small changes in various parameters. After the element has been reduced considerably in size, an originally allowable error of a condition for the fabrication procedure may bring a great effect on performances of the element. Therefore, the requirements on the fabrication processes will necessarily tend to be demanding so as to achieve a good performance of the element.
The CMP process was introduced into the Integrated Circuit (IC) fabrication industry by IBM Corp. in 1984. Firstly, it was used for planarization of an inter-metal isolation dielectric (IMD) in a later process, and then was used for planarization of tungsten (W) thanks to apparatus and process improvements. Next, it was used for planarization of Shallow Trench Isolation (ISO) and copper (Cu). The CMP process is one technology with the most rapid growth and being paid most attention in the IC fabrication procedure.
At present, a precise computer control has been enabled fully for the CMP process. Unfortunately, during an operation of a CMP apparatus, a failure of a computer or control software may occur, such as a crash of the computer, a halt of the operation of the control software, an instruction error of the control software or the like, which can result in a stop of the operation of the CMP apparatus or in over-polishing a wafer. In the process conditions of the prior art, the apparatus can not alarm automatically when any of these failures occurs, and it is difficult for a maintenance staff to discover and obviate the failure upon occurring, which can give rise to a large number of direct wafer rejects in the CMP apparatus and thus effect the qualification rate.
In addition to this, a situation may occur although rarely in which a computer control system or the CMP apparatus is powered off unexpectedly, thus resulting in a stop of the operation of the apparatus. In such a case, wafers for which the CMP has not been finished may remain and thus may be eroded in a polishing liquid. If the apparatus failure can be discovered in a timely way, those wafers can be removed duly, and the loss due to the eroded wafers can be avoided. In this case, however, an alarm device if any would not work due to the system entirely powered off.
Similarly to the CMP process, the same cases may occur in other fabrication processes where a failure of the computer system or operation software controlling the operation of the apparatus can cause a failure of the operation of the apparatus as well as where the system entirely powered off can cause a failure of the operation of the apparatus. Currently, there is no a satisfactory control method in this regard.